1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly to an operational amplifier capable of suppressing occurrence of overshootor undershoot to the minimum.
2. Description of the Prior Art
As an operational amplifier which can handle input and output in a wide range and drive a large load, up to now, there has been a technique disclosed in Japanese Patent Publication No.Hei 9-93,055 by the present inventors.
An operational amplifier disclosed in Japanese Patent Publication No.Hei 9-93,055 is described with reference to FIG. 10. The operational amplifier is provided with an input stage K1, a driving stage K2 and an output stage K3.
First, the composition of the input stage K1 of the operational amplifier is described. The input stage K1 of the operational amplifier is provided with P channel field effect transistors (FETs) M1 and M2, N channel FETs M5 and M6, a P channel FET for constant current source M41, an N channel FET for constant current source M42, N channel FETs M3 and M9, N channel FETs M4 and M10, and P channel FETs M7 and M8. The P channel FETs M1 and M2, whose sources are commonly connected to each other and whose gates are respectively to signal input terminals 1 and 2, form a differential transistor couple. The N channel FETs M5 and M6, whose sources are commonly connected to each other and whose gates are respectively to signal input terminals 1 and 2, form a differential transistor couple. The P channel FET for constant current source M41 is connected between the sources of the P channel FETs M1 and M2 commonly connected to each other and a high level side power source terminal 5.
The N channel FET for constant current source M42 is connected between the sources of the N channel FETs M5 and M6 commonly connected to each other and a low level side power source terminal 4. In the N channel FET M3, its gate and drain are connected to the drain of the P channel FET M1 and its source is connected to the low level side power source terminal 4. In an N channel FET M9, its drain is connected to the connection point of the drain of the N channel FET M6 and the drain of the P channel FET M7, and its source is connected to the low level side power source terminal 4. The N channel FETs M3 and M9 form a first current mirror circuit. In an N channel FET M4, its drain and gate are connected to the drain of the P channel FET M2 and its source is connected to the low level side power source terminal 4.
In an N channel FET M10, its drain is connected to the connection point of the drain of the N channel FET M5 and the drain of the P channel FET M8, and its source is connected to the low level side power source terminal 4.
The N channel FETs M4 and M10 form a second current mirror circuit. The P channel FETs M7 and M8 are connected respectively between the drain of the N channel FET M6 and the high level side power source terminal 5 and between the drain of the N channel FET M5 and the high level side power source terminal 5.
The P channel FETs M7 and M8 form a current mirror circuit for acting as an active load.
Next, the composition of the driving stage K2 of the operational amplifier is described.
The driving stage K2 of the operational amplifier is provided with P channel FETs M20, M21 and M22, and N channel FETs for constant current power source M43 and M44.
The N channel FETs for constant current source M43 and M44 both have their sources connected to the low level side power source terminal 4. The N channel FETs for constant current source M43 and M44 both are of a current-intake type.
In the P channel FET M20, its source is connected to the high level side power source terminal 5, its gate is connected to the connection point of the drain of the N channel FET M5 and the drain of the P channel FET M8, and its drain is connected to the drain of the N channel FET for constant current power source M43. In the P channel FET M21, its source is connected to the high level side power source terminal 5, its gate is connected to the drain of the P channel FET M20, and its drain is connected to the gate of the P channel FET M22. In the P channel FET M22, its source is connected to the high level side power source terminal 5, its gate is connected to the connection point of the drain of the P channel FET M20 and the drain of the P channel FET M21, and its drain is connected to the drain of the N channel FET for constant current power source M44. Next, the composition of the output stage K3 of the operational amplifier is described.
The output stage K3 of the operational amplifier is provided with a P channel FET M23 and an N channel FET M24. In the P channel FET M23, its source is connected to the high level side power source terminal 5, its gate is connected to the connection point of the drain of the N channel FET M5 and the drain of the P channel FET M8, and its drain is connected to the output signal terminal 3. In the N channel FET M24, its source is connected to the low level side power source terminal 4, its gate is connected to the connection point of the drain of the P channel FET M22 and the drain of the N channel FET for constant current power source M44, and its drain is connected to the output signal terminal 3.
Next, operation of the operational amplifier shown in FIG. 10 is described. The operational amplifier shown in FIG. 10 has the input stage K1 of a wide input range made by connecting in parallel with each other a differential transistor couple composed of the P channel FETs M1 and M2 and a differential transistor couple composed of the N channel FETs M5 and M6. The operational amplifier changes the gate voltage of the P channel FET M23 according to the ratio of signal voltages respectively applied to the signal input terminals 1 and 2. And a signal passing through the P channel FETs M20, M21 and M22 changes the gate voltage of the N channel FET M24. The potential of the output signal terminal 3 is quickly raised or dropped according to variation quantities of the respective gate voltages of the P channel FET M23 and the N channel FET M24.
First, the case where a voltage applied to the signal input terminal 1 is higher than a voltage applied to the signal input terminal 2 is described. The voltage of the connection point of the drain of the N channel FET M5, the drain of the P channel FET M8 and the drain of the N channel FET M1O, namely, the gate voltage of the P channel FETs M20 and M23 becomes low. At this time, an electric current which flows from the high level side power source terminal 5 through the P channel FET M23 to the output signal terminal 3 becomes large. And at this time, the voltage of the connection point of the drain of the P channel FET M20 and the drain of the N channel FET for constant current power source M43, namely, the gate voltage of the P channel FETs M21 and M22 becomes high. Hereupon, the voltage of the connection point of the drain of the P channel FET M22 and the drain of the N channel FET for constant current power source M44, namely, the gate voltage of the N channel FET M24 becomes low.
At this time, an electric current flowing from the output signal terminal 3through the M channel FET M24 to the low level side power source terminal 4 becomes very small. That is to say, since an electric current flowing through the N channel FET M24 is in a shutoff state, an electric current flowing from the high level side power source terminal 5 through the P channel FET M23 can quickly raise the potential of the output signal terminal 3 by flowing to the output signal terminal 3 (when charging).
On the other hand, the case where a voltage applied to the signal input terminal 1 is lower than a voltage applied to the signal input terminal 2 is described. The voltage of the connection point of the drain of the N channel FET M5, the drain of the P channel FET M8 and the drain of the N channel FET M10, namely, the gate voltage of the P channel FETs M20 and M23 becomes high.
At this time, an electric current which flows from the high level side power source terminal 5 through the P channel FET M23 to the output signal terminal 3 becomes very small. And at the same time as this, the voltage of the connection point of the drain of the P channel FET M20 and the drain of the N channel FET for constant current power source M43, namely, the gate voltage of the P channel FETs M21 and M22 becomes low. Hereupon, the voltage of the connection point of the drain of the P channel FET M22 and the drain of the N channel FET for constant current power source M44, namely, the gate voltage of the N channel FET M24 becomes high. At this time, an electric current flowing from the output signal terminal 3 through the N channel FET M24 to the low level side power source terminal 4 becomes large. At this time, an electric current flowing from the output signal terminal 3 through the N channel FET M24 to the low level side power source terminal 4 is shut off. That is to say, it is possible to quickly lower the potential of the output signal terminal 3 by making a large electric current flow from the output signal terminal 3 through the N channel FET M24 to the low level side power source terminal 4 (when discharging). Furthermore, this operational amplifier can provide the output stage K3 of a wide output range which can output the potential of the output signal terminal 3 ranging from a potential lowered by the voltage between the drain and source of the P channel FET M23 from the high level side power source terminal 5 to a potential raised by the voltage between the drain and source of the N channel FET M24 from the low level side power source terminal 4.
And when the potential of the output signal terminal 3 is lowered, the gate potential of the P channel FET M23 and the gate potential of the P channel FET M20 both rise, but since the drain of the P channel FET M20 is connected to the N channel FET for constant current power source M43, a through current corresponding to a discharging current does not flow. Since an idling current to flow through the P channel FET M23 and the N channel FET M24 in a balanced state (in a state where the potential of the output signal terminal 3 has reached a target potential) is determined by the ratio in transistor size of the P channel FET M20 to the P channel FET M23 and the N channel FET for constant current power source M43, variation of a threshold value does not influence the idling current.
As described above, the operational amplifier of FIG. 10 has a wide input range and a wide output range and can quickly raise or lower the potential of the output signal terminal 3, and its idling current is not influenced by the absolute variation in threshold value of transistors and said operational amplifier can suppress occurrence of a through current according to a discharging current to flow inside it at the time of discharging. According to the composition of FIG. 10, up to now, there has been a problem that the P channel FET M23 and the N channel FET M24 are different from each other in amplification factor and transfer delay of input signals since the input signals pass through different transfer paths.
That is to say, the P channel FET M23 has a signal inputted directly from the input stage output terminal A1. On the other hand, the N channel FET M24 has a signal of the input stage output terminal A1 inputted through the P channel FETs M20, M21 and M22.
Accordingly, when comparing the P channel FET M23 and the N channel FET M24 with each other in input timing of an input signal from the input stage output terminal A1, the N channel FET M24 has a more delayed signal inputted. And when comparing the P channel FET M23 and the N channel FET M24 with each other in amplification factor of an input signal from the input stage output terminal A1, the N channel FET M24 has a more greatly amplified signal inputted than a signal inputted to the P channel FET M23 due to a fact that the former is inputted through the P channel FETs M20, M21 and M22.
Particularly at the time of discharging, there has been a problem that since an input signal to the N channel FET M24 is more delayed in input timing and is more greatly amplified than a signal inputted to the P channel FET M23, the time of releasing the N channel FET M24 from a shutoff state is delayed and no current flows through the N channel FET M24 during the period of delay and therefore an overshoot phenomenon is liable to occur.
An overshoot or undershoot phenomenon in waveform outputted to the output signal terminal 3 has been sometimes caused by difference in delay time and amplification factor between inputted signals.
In case of using such an operational amplifier as described above as a LCD driver for example, a plurality of operational amplifiers corresponding to the number of pixels of the LCD is needed. In this case the LCD screen sometimes becomes irregular in display quality due to a fact that the respective operational amplifiers are different from one another in occurrence or magnitude of overshoot or undershoot.